Differences

This shows you the differences between two versions of the page.

--- linux:system:power-management:aspm [2025/09/22 15:23] – oscar
+++ linux:system:power-management:aspm [2025/09/22 15:25] (current) – [Power Mode L0 and L1] oscar
@@ Line 8: / Line 8: @@
 Two low power states are defined in PCIe: L0s and L1 as below:
-  * L0s low power Link state is optimized for short entry and exit latencies, while providing substantial power savings."
+  * L0: low power Link state is optimized for short entry and exit latencies, while providing substantial power savings. It concerns setting low power mode for one direction of the serial link only, usually downstream of the PHY controller.
-  * L1 Link state is optimized for maximum power savings at a cost of longer entry and exit latencies."
+  * L1: Link state is optimized for maximum power savings at a cost of longer entry and exit latencies. It is bidirectional and results in greater power reductions though with the penalty of greater exit latency.
-The first mode (L0s) concerns setting low power mode for one direction of the serial link only, usually downstream of the PHY controller. The second mode (L1) is bidirectional and results in greater power reductions though with the penalty of greater exit latency.
 PCIE cards should always support ASPM, what the ASPM requirements says today is that L1 is mandatory and L0s is optional unless the formfactor specifications explicitly requies it. Not sure which form factors explicitly require L0s (anyone?). Additionally software must not enable L0s in either direction on a given Link unless components on both sides of the Link each support L0s.