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linux:system:power-management:aspm [2025/09/22 15:20] – [Links] oscarlinux:system:power-management:aspm [2025/09/22 15:25] (current) – [Power Mode L0 and L1] oscar
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 ====== ASPM on Linux ====== ====== ASPM on Linux ======
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 +----
 +
 ASPM is a PCI-E enhancement. It allows for a device to go completely into electrically idle state, meaning it will not send or receive electrical signals for a while. While ASPM brings a reduction in power consumption, it can also result in increased latency as the serial bus needs to be 'woken up' from low-power mode, possibly reconfigured and the host-to-device link re-established. This is known as ASPM exit latency and takes up valuable time which can be annoying to the end user if it is too obvious when it occurs. This may be acceptable for mobile computing, however, when battery life is critical. ASPM is a PCI-E enhancement. It allows for a device to go completely into electrically idle state, meaning it will not send or receive electrical signals for a while. While ASPM brings a reduction in power consumption, it can also result in increased latency as the serial bus needs to be 'woken up' from low-power mode, possibly reconfigured and the host-to-device link re-established. This is known as ASPM exit latency and takes up valuable time which can be annoying to the end user if it is too obvious when it occurs. This may be acceptable for mobile computing, however, when battery life is critical.
 ===== Power Mode L0 and L1 ===== ===== Power Mode L0 and L1 =====
-Currently, two low power modes are specified by the PCIe 2.0 specification; L0s and L1 mode. The first mode (L0sconcerns setting low power mode for one direction of the serial link only, usually downstream of the PHY controller. The second mode (L1is bidirectional and results in greater power reductions though with the penalty of greater exit latency. +Currently, two low power modes are specified by the PCIe 2.0 specification; L0s and L1 mode.  
 +Two low power states are defined in PCIe: L0s and L1 as below: 
 + 
 +  * L0: low power Link state is optimized for short entry and exit latencies, while providing substantial power savings. It concerns setting low power mode for one direction of the serial link only, usually downstream of the PHY controller. 
 +  * L1: Link state is optimized for maximum power savings at a cost of longer entry and exit latencies. It is bidirectional and results in greater power reductions though with the penalty of greater exit latency. 
  
 PCIE cards should always support ASPM, what the ASPM requirements says today is that L1 is mandatory and L0s is optional unless the formfactor specifications explicitly requies it. Not sure which form factors explicitly require L0s (anyone?). Additionally software must not enable L0s in either direction on a given Link unless components on both sides of the Link each support L0s. PCIE cards should always support ASPM, what the ASPM requirements says today is that L1 is mandatory and L0s is optional unless the formfactor specifications explicitly requies it. Not sure which form factors explicitly require L0s (anyone?). Additionally software must not enable L0s in either direction on a given Link unless components on both sides of the Link each support L0s.
linux/system/power-management/aspm.1758554422.txt.gz · Last modified: by oscar